At least the problem seems correctable. The DRAM controller would need to have an upper bound on the amount of time it'll keep RAS selected for a single row. Might even be possible with a firmware update as I understand that DRAM training/control is a horror of fragile, poorly understood, closed source software.
Edit: So reading further on, this is covered in section 7.3 "Limiting the Maximum Row-Open Time"
Ultimately the complexity of managing all these DRAM corner cases needs to be handled inside the DRAM itself as there's just no way for DRAM controllers to be revised to cope with every new and exciting DRAM hardware bug. Sadly, the DRAM vendors continue to get away with publishing specs for their hardware that the hardware doesn't meet. Once upon a time that would result in a recall.
It looks like they were testing this at at least 50C, which IMHO is far too hot for RAM to be.
I wonder what the industry response to this will be. RowHammer was memorable because they managed to convince one widely-used memory testing tool to not run the tests by default because too many systems would fail.
Regardless of access pattern, if you can get memory to not read back exactly what was written to that address, the hardware is just plain broken.
I found a Micron datasheet that specifies that (some of?) their commercial DDR5 modules are specified for operation up to 95°C, though the refresh rate must be doubled above 85°C. (https://media-www.micron.com/-/media/client/global/documents... page 13)
Typically commercial RAM has a temp range of 0 to 85degC. In the olden days, you constrained your IO timing on the device/chip that drove the ram so that it worked at all temperatures at the rated speed. (Well, unless you were a 90s graphics card integrator...)
Now, at least since DDR3, PVT variations are continually calibrated out at runtime. So as the temp goes up, you still get periodic, quick recalibration.
DDR4 and now 5 have even more extensive compensation to keep the electrons flowing at the edges of our current ability. Did you know that GDDR5 has had the ability to CRC data bursts since 2008? Now it's come down to normal memory.
Edit: So reading further on, this is covered in section 7.3 "Limiting the Maximum Row-Open Time"